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Ferroelectric Schottky Barrier MOSFET as Analog Synapses for Neuromorphic Computing.

, , , , , , and . ESSCIRC, page 121-124. IEEE, (2022)

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Comparison between WKB and Wavelet Approach for Analytical Calculation of Tunneling Currents in Schottky Barrier Field-Effect Transistors., , , , and . MIXDES, page 31-36. IEEE, (2023)Experimental characterization of the static noise margins of strained silicon complementary tunnel-FET SRAM., , , , , , , and . ESSDERC, page 42-45. IEEE, (2017)NEUROTEC I: Neuro-inspired Artificial Intelligence Technologies for the Electronics of the Future., , , , , , , , , and 23 other author(s). DATE, page 957-962. IEEE, (2022)Experimental demonstration of improved analog device performance in GAA-NW-TFETs., , , , , and . ESSDERC, page 178-181. IEEE, (2014)Experimental and Theoretical Analysis of Stateful Logic in Passive and Active Crossbar Arrays for Computation-in-Memory., , , , , , , , and . ISCAS, page 2792-2796. IEEE, (2022)Ultrathin lateral unidirectional bipolar-type insulated-gate transistor as pH sensor., , , , , , and . ESSDERC, page 268-271. IEEE, (2017)Ferroelectric Schottky Barrier MOSFET as Analog Synapses for Neuromorphic Computing., , , , , , and . ESSCIRC, page 121-124. IEEE, (2022)High Performance 5 nm Si Nanowire FETs with a Record Small SS = 2.3 mV/dec and High Transconductance at 5.5 K Enabled by Dopant Segregated Silicide Source/Drain., , , , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)Low frequency noise in strained silicon nanowire array MOSFETs and Tunnel-FETs., , , , , , , , , and 2 other author(s). ESSDERC, page 256-259. IEEE, (2013)GeSn Vertical Gate-all-around Nanowire n-type MOSFETs., , , , , , , , and . ESSDERC, page 364-367. IEEE, (2022)