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Precision tunable RTL macro-modelling cycle-accurate power estimation., and . IET Comput. Digit. Tech., 5 (2): 95-103 (2011)Efficient Functional Locking of Behavioral IPs., and . MWSCAS, page 639-642. IEEE, (2020)Autonomous temperature control technique in VLSI circuits through logic replication., and . IET Comput. Digit. Tech., 3 (1): 62-71 (2009)CERTIFY: AutomatiC MEasuRing The QualIty oF High-Level SYnthesis., , and . ISCAS, page 1-5. IEEE, (2023)Investigation and Optimization of Pin Multiplexing in High-Level Synthesis., , and . ACM Great Lakes Symposium on VLSI, page 427-430. ACM, (2018)PEPA: Performance Enhancement of Embedded Processors through HW Accelerator Resource Sharing., and . ACM Great Lakes Symposium on VLSI, page 23-28. ACM, (2023)Functional Obfuscation of Hardware Accelerators through Selective Partial Design Extraction onto an Embedded FPGA., , , , , , , and . ACM Great Lakes Symposium on VLSI, page 171-176. ACM, (2019)DEEP: Dedicated Energy-Efficient Approximation for Dynamically Reconfigurable Architectures., and . ICCD, page 587-594. IEEE Computer Society, (2018)Accelerating FPGA Prototyping through Predictive Model-Based HLS Design Space Exploration., , and . DAC, page 97. ACM, (2019)Hardware Trojan avoidance and detection for dynamically re-configurable FPGAs., and . FPT, page 193-196. IEEE, (2016)