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Proposal, analysis and demonstration of Analog/Digital-mixed Neural Networks based on memristive device arrays., , , , and . ISCAS, page 1-5. IEEE, (2018)7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme., , , , , , , , , and 3 other author(s). ISSCC, page 132-133. IEEE, (2016)Very low-voltage swing while high-bandwidth data transmission through 4096 bit TSVs., , and . 3DIC, page 1-4. IEEE, (2013)Circuit And Systems Based on Advanced MRAM for Near Future Computing Applications., , , and . VLSI Circuits, page 278-. IEEE, (2019)7.5 A 3.3ns-access-time 71.2μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture., , , , , , , , , and 1 other author(s). ISSCC, page 1-3. IEEE, (2015)18.7 A DC to 35MHz Fully Integrated Single-Power-Supply Isolation Amplifier for Current- and Voltage-Sensing Front-Ends of Power Electronics., , and . ISSCC, page 298-300. IEEE, (2020)Physically unclonable function using initial waveform of ring oscillators on 65 nm CMOS technology., , , , , , , and . CoRR, (2017)Accurate analysis of substrate sensitivity of active transistors in an analog circuit., , , , , , , , and . ISQED, page 56-61. IEEE, (2011)A 100GB/s wide I/O with 4096b TSVs through an active silicon interposer with in-place waveform capturing., , , , , , and . ISSCC, page 434-435. IEEE, (2013)12.4 A 1mm-pitch 80×80-channel 322Hz-frame-rate touch sensor with two-step dual-mode capacitance scan., , , , , , , , and . ISSCC, page 216-217. IEEE, (2014)