( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators.

, , , , , , и . CoRR, (2020)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Thilo Pionteck

Jürgen Pionteck

Hans Thilow

Heinz Thilo

Detlev Thilo-Körner

 

Другие публикации лиц с тем же именем

Adaptive allocation of default router paths in Network-on-Chips for latency reduction., , и . HPCS, стр. 140-147. IEEE, (2016)A simulation environment for design space exploration for asymmetric 3D-Network-on-Chip., , , , и . ReCoSoC, стр. 1-8. IEEE, (2016)Ratatoskr: An open-source framework for in-depth power, performance and area analysis in 3D NoCs., , , , , и . CoRR, (2019)Continuous live-tracing as debugging approach on FPGAs., , , и . ReConFig, стр. 1-8. IEEE, (2017)A cycle-accurate Network-on-Chip simulator with support for abstract task graph modeling., и . ISSoC, стр. 1-6. IEEE, (2014)Design of a reconfigurable AES encryption/decryption engine for mobile terminals., , , , и . ISCAS (2), стр. 545-548. IEEE, (2004)Integration dynamisch rekonfigurierbarer Funktionseinheiten in Prozessoren., , , , и . ARCS Workshops, том P-41 из LNI, стр. 155-164. GI, (2004)Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators., , , , , , и . ISQED, стр. 60-66. IEEE, (2021)Teaching Informatics Students the Secrets of Hardware Design.. MSE, стр. 31-32. IEEE Computer Society, (2007)Coding-aware Link Energy Estimation for 2D and 3D Networks-on-Chip with Virtual Channels., , , , и . PATMOS, стр. 222-228. IEEE, (2018)