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Gate-Delay-Fault Testability Properties of Multiplexor-Based Networks., , и . ITC, стр. 887-896. IEEE Computer Society, (1991)Challenges in code generation for embedded processors., , , , , , , и . Code Generation for Embedded Processors, стр. 48-64. Kluwer, (1994)MARTHA: architecture for control and emulation of power electronics and smart grid systems., , , и . DATE, стр. 519-524. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Aegis: A Single-Chip Secure Processor., , и . IEEE Des. Test Comput., 24 (6): 570-580 (2007)Performance metrics and empirical results of a PUF cryptographic key generation ASIC., , , , и . HOST, стр. 108-115. IEEE Computer Society, (2012)Integrity verification for path Oblivious-RAM., , , , и . HPEC, стр. 1-6. IEEE, (2013)Virtual monotonic counters and count-limited objects using a TPM without a trusted OS., , , , и . STC, стр. 27-42. ACM, (2006)Delay Computation in Combinational Logic Circuits: Theory and Algorithms., , и . ICCAD, стр. 176-179. IEEE Computer Society, (1991)Verification of Relations Between Synchronous Machines., , и . ICCAD, стр. 380-383. IEEE Computer Society, (1991)Synthesis of hazard-free multi-level logic under multiple-input changes from binary decision diagrams., и . ICCAD, стр. 542-549. IEEE Computer Society / ACM, (1994)