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Concurrent error detection in Reed Solomon decoders., , , and . ISCAS, IEEE, (2006)Fault Localization, Error Correction, and Graceful Degradation in Radix 2 Signed Digit-Based Adders., , , , and . IEEE Trans. Computers, 55 (5): 534-540 (2006)Grid Generation and Verification for 3-D Device Simulation., , and . EUROSIM, page 517-522. Elsevier, (1992)A Self Checking Reed Solomon Encoder: Design and Analysis., , , and . DFT, page 111-119. IEEE Computer Society, (2005)Design and Evaluation of a Hardware on-line Program-Flow Checker for Embedded Microcontrollers., , , and . DFT, page 371-379. IEEE Computer Society, (2006)Self Checking Circuit Optimization by means of Fault Injection Analysis: A Case Study on Reed Solomon Decoders., , , , , , and . IOLTS, page 194-196. IEEE Computer Society, (2007)System-on-Chip Oriented Fault-Tolerant Sequential Systems Implementation Methodology., , , , , and . DFT, page 455-460. IEEE Computer Society, (2001)A Fault-Tolerant 176 Gbit Solid State Mass Memory Architecture., , , and . DFT, page 173-. IEEE Computer Society, (2000)A fault tolerant hardware based file system manager for solid state mass memory., , , , and . ISCAS (5), page 649-652. IEEE, (2003)Development of a dynamic routing system for a fault tolerant solid state mass memory., , , , and . ISCAS (4), page 830-833. IEEE, (2001)