Author of the publication

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

An 8.8 TFLOPS/W Floating-Point RRAM-Based Compute-in-Memory Macro Using Low Latency Triangle-Style Mantissa Multiplication.

X. Hu, Y. Wang, Z. Ma, G. Wen, Z. Wang, Z. Lu, Y. Liu, Y. Li, X. Liang, X. Zeng, and Y. Xie. IEEE Trans. Circuits Syst. II Express Briefs, 70 (11): 4216-4220 (November 2023)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Jun Hu

Zaijun Hu

Bing Hu

Hu Wang

Ruguo Hu

Other publications of authors with the same name

GCFP-ACIM: A 40nm 4.74TFLOPS/W General Complex Float-Point Analog Compute-in-Memory with Adaptive Power-Saving for HDR Signal Processing Applications.Z. Ma, X. Hu, G. Wen, Y. Wang, Z. Wang, Y. Lin, Y. Wang, Y. Guo, Y. Li, X. Liang and 2 other author(s). A-SSCC, page 1-3. IEEE, (2023)A Semi-Floating Gate Transistors In-Memory Computing design with 40.14 TOPS/W for matrix-multiplication with frequently updated weight.Y. Lin, Y. Wang, X. Hu, J. Feng, G. Wen, X. Xiong, H. Tian, and Y. Xie. ASICON, page 1-4. IEEE, (2021)The Establishment of Supply Chain with Game Model of Competition and Cooperation.X. Hu. J. Softw., 7 (3): 670-677 (2012)An 8.8 TFLOPS/W Floating-Point RRAM-Based Compute-in-Memory Macro Using Low Latency Triangle-Style Mantissa Multiplication.X. Hu, Y. Wang, Z. Ma, G. Wen, Z. Wang, Z. Lu, Y. Liu, Y. Li, X. Liang, X. Zeng and 1 other author(s). IEEE Trans. Circuits Syst. II Express Briefs, 70 (11): 4216-4220 (November 2023)A 40nm 150 TOPS/W High Row-Parallel MRAM Compute-in-Memory Macro with Series 3T1MTJ Bitcell for MAC Operation.Z. Ma, X. Hu, Y. Wang, G. Wen, X. Zeng, and Y. Xie. ISCAS, page 1-5. IEEE, (2023)A High Area-Efficiency RRAM-Based Strong PUF with Multi-Entropy Source and Configurable Double-Read Process.X. Hu, Y. Wang, J. Feng, Z. Ma, X. Zeng, and Y. Xie. ISCAS, page 2438-2442. IEEE, (2022)An 8Kb 40-nm 2T2MTJ STT-MRAM Design with 2.6ns Access Time and Time-Adjustable Writing Process.X. Hu, D. Li, Y. Wang, J. Feng, Z. Ma, S. Wang, T. Min, X. Zeng, and Y. Xie. ASICON, page 1-4. IEEE, (2021)A digitalized RRAM-based Spiking Neuron Network system with 3-bit weight and unsupervised online learning scheme.D. Wu, S. Yan, H. Tang, Y. Wang, J. Feng, X. Hu, J. Cao, and Y. Xie. ASICON, page 1-4. IEEE, (2019)

BibSonomy

Disambiguation of "Hu, Xianwu"

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

An 8.8 TFLOPS/W Floating-Point RRAM-Based Compute-in-Memory Macro Using Low Latency Triangle-Style Mantissa Multiplication.

Please choose a person to relate this publication to

Jun Hu

Zaijun Hu

Bing Hu

Hu Wang

Ruguo Hu

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Hu, Xianwu"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML An 8.8 TFLOPS/W Floating-Point RRAM-Based Compute-in-Memory Macro Using Low Latency Triangle-Style Mantissa Multiplication.

Please choose a person to relate this publication to

Jun Hu

Zaijun Hu

Bing Hu

Hu Wang

Ruguo Hu

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

An 8.8 TFLOPS/W Floating-Point RRAM-Based Compute-in-Memory Macro Using Low Latency Triangle-Style Mantissa Multiplication.