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Disambiguation of "Zeng, Xiaoyang"

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A 40nm 150 TOPS/W High Row-Parallel MRAM Compute-in-Memory Macro with Series 3T1MTJ Bitcell for MAC Operation.

, , , , , and . ISCAS, page 1-5. IEEE, (2023)

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Xiaoyang Wang

Xiaoyang Gao

Gang Zeng

Lecai Zeng

Jin Zeng

 

Other publications of authors with the same name

A highly pipelined VLSI architecture for all modes and block sizes intra prediction in HEVC encoder., , , , and . ASICON, page 1-4. IEEE, (2013)A 2D mesh NoC with self-configurable and shared-FIFOs routers., , , , and . ASICON, page 1-4. IEEE, (2013)A fast multi-core virtual platform and its application on software development., , , , and . ASICON, page 1-4. IEEE, (2013)Low-complexity two-stage timing acquisition scheme for UWB communications., , and . WTS, page 53-56. IEEE, (2008)An improved coarse synchronization scheme in 3GPP LTE downlink OFDM systems., , , , and . ISCAS, page 1516-1519. IEEE, (2012)A 65nm 39GOPS/W 24-core processor with 11Tb/s/W packet-controlled circuit-switched double-layer network-on-chip and heterogeneous execution array., , , , , , , , , and 4 other author(s). ISSCC, page 56-57. IEEE, (2013)A low power register file with asynchronously controlled read-isolation and software-directed write-discarding., , , , and . ISCAS, page 349-352. IEEE, (2013)Modeling of a double-sampling switched-capacitor bandpass delta-sigma modulator for multi-standard applications., , , , and . ASICON, page 465-468. IEEE, (2011)Low power design for FIR filter., , , and . ASICON, page 1-4. IEEE, (2013)Two-dimensional Parity-based Concurrent Error Detection Method for AES Algorithm against Differential Fault Attack and its VLSI Implementation., , , and . SiPS, page 151-156. IEEE, (2007)