( en | de | ru )

 

Disambiguation of "Bagherzadeh, Nader"

Author of the publication

copydeleteadd this publication to your clipboard
On Design and Performance Analysis of a Superscalar Architecture.

, , and . ICPP (1), page 171-178. CRC Press, (1992)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Hassan Bagherzadeh

Nader Tawassoli

Faramarz Nader

Nader Purnaqchéband

Nader Ahmad

 

Other publications of authors with the same name

Network Facility for a Reconfigurable Computer Architecture., , , , and . ICDCS, page 264-271. IEEE Computer Society, (1985)Fast parallel soft Viterbi decoder mapping on a reconfigurable DSP platform., , , and . SoCC, page 3-6. IEEE, (2004)Efficient Mitchell's Approximate Log Multipliers for Convolutional Neural Networks., , , , and . IEEE Trans. Computers, 68 (5): 660-675 (2019)Near-optimal message routing and broadcasting in faulty hypercubes., and . Int. J. Parallel Program., 19 (5): 405-423 (1990)Performance of symbolic applications on a parallel architecture., , , and . Int. J. Parallel Program., 16 (3): 183-214 (1987)Voltage mirror circuit by carbon nanotube field effect transistors for mirroring dynamic random access memories in multiple-valued logic and fuzzy logic., , , and . IET Circuits Devices Syst., 9 (5): 343-352 (2015)A Multi-Standard Viterbi Decoder for Mobile Applications Using a Reconfigurable Architecture., , and . VTC Fall, page 1-5. IEEE, (2006)A scalable delay insensitive asynchronous NoC with adaptive routing., , and . ICT, page 995-1002. IEEE, (2010)Flow mapping and data distribution on mesh-based deep learning accelerator., , , , and . NOCS, page 13:1-13:8. ACM, (2019)Partition Pruning: Parallelization-Aware Pruning for Dense Neural Networks., , , and . PDP, page 307-311. IEEE, (2020)