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Memristor-based synapse design and a case study in reconfigurable systems., , , , and . IJCNN, page 1-6. IEEE, (2013)ReSiPE: ReRAM-based Single-Spiking Processing-In-Memory Engine., , and . DAC, page 1-6. IEEE, (2020)Accelerating graph computation with racetrack memory and pointer-assisted graph representation., , , and . DATE, page 1-4. European Design and Automation Association, (2014)Array Organization and Data Management Exploration in Racetrack Memory., , , , and . IEEE Trans. Computers, 65 (4): 1041-1054 (2016)SiDA: Sparsity-Inspired Data-Aware Serving for Efficient and Scalable Large Mixture-of-Experts Models., , , , , , , , , and . CoRR, (2023)RED: A ReRAM-based Deconvolution Accelerator., , , , and . DATE, page 1763-1768. IEEE, (2019)Neural Predictor for Neural Architecture Search., , , , , and . ECCV (29), volume 12374 of Lecture Notes in Computer Science, page 660-676. Springer, (2020)Learning Efficient Sparse Structures in Speech Recognition., , , , , and . ICASSP, page 2717-2721. IEEE, (2019)ZARA: A Novel Zero-free Dataflow Accelerator for Generative Adversarial Networks in 3D ReRAM., , , and . DAC, page 133. ACM, (2019)Exploration of GPGPU Register File Architecture Using Domain-wall-shift-write based Racetrack Memory., , , , and . DAC, page 196:1-196:6. ACM, (2014)