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Disambiguation of "Giraud, Bastien"

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Experimental demonstration of Single-Level and Multi-Level-Cell RRAM-based In-Memory Computing with up to 16 parallel operations.

, , , , , , , , , and . IRPS, page 8-1. IEEE, (2022)

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Volker Giraud

Reinhard Giraud

Bastien Pietropaoli

Bastien Clausse

Xavier Giraud

 

Other publications of authors with the same name

Binary Linear ECCs Optimized for Bit Inversion in Memories with Asymmetric Error Probabilities., , and . DATE, page 298-301. IEEE, (2020)Smart instruction codes for in-memory computing architectures compatible with standard SRAM interfaces., , , , and . DATE, page 1634-1639. IEEE, (2018)Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs., , , , , , , , , and 10 other author(s). DATE, page 613-618. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Storage Class Memory with Computing Row Buffer: A Design Space Exploration., , , , , , , , , and . DATE, page 1-6. IEEE, (2021)Capacitor based SneakPath compensation circuit for transistor-less ReRAM architectures., , , , and . NANOARCH, page 7-12. ACM, (2016)High density emerging resistive memories: What are the limits?, , , , and . LASCAS, page 1-4. IEEE, (2017)Benefits of Design Assist Techniques on Performances and Reliability of a RRAM Macro., , , , , , , , , and 9 other author(s). IMW, page 1-4. IEEE, (2023)Technology variability from a design perspective., , , , , and . CICC, page 1-8. IEEE, (2010)SRAM Voltage and Current Sense Amplifiers in sub-32nm Double-gate CMOS Insensitive to Process Variations and Transistor Mismatch., , , , and . ISCAS, page 3170-3173. IEEE, (2009)Optimization of a voltage sense amplifier operating in ultra wide voltage range with back bias design techniques in 28nm UTBB FD-SOI technology., , , , and . ICICDT, page 53-56. IEEE, (2013)