Author of the publication

Value-Aware Error Detection and Correction for SRAM Buffers in Low-Bitwidth, Floating-Point CNN Accelerators.

, , and . ASP-DAC, page 242-247. ACM, (2021)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors., , , , , , , , , and 7 other author(s). ISSCC, page 494-496. IEEE, (2018)DrowsyNet: Convolutional neural networks with runtime power-accuracy tunability using inference-stage dropout., , , , and . VLSI-DAT, page 1-4. IEEE, (2018)A 1Mb Multibit ReRAM Computing-In-Memory Macro with 14.6ns Parallel MAC Computing Time for CNN Based AI Edge Processors., , , , , , , , , and 12 other author(s). ISSCC, page 388-390. IEEE, (2019)Considerations Of Integrating Computing-In-Memory And Processing-In-Sensor Into Convolutional Neural Network Accelerators For Low-Power Edge Devices., , , , , , , , , and 3 other author(s). VLSI Circuits, page 166-. IEEE, (2019)VST: A virtual stress testing framework for discovering bugs in SSD flash-translation layers., , and . ICCAD, page 283-290. IEEE, (2017)A 0.8 V Intelligent Vision Sensor With Tiny Convolutional Neural Network and Programmable Weights Using Mixed-Mode Processing-in-Sensor Technique for Image Classification., , , , , , , and . IEEE J. Solid State Circuits, 58 (11): 3266-3274 (November 2023)Physically Tightly Coupled, Logically Loosely Coupled, Near-Memory BNN Accelerator (PTLL-BNN)., , , , , , , and . ESSCIRC, page 241-244. IEEE, (2019)5.9 A 0.8V Multimode Vision Sensor for Motion and Saliency Detection with Ping-Pong PWM Pixel., , , , , , , , , and 3 other author(s). ISSCC, page 110-112. IEEE, (2020)Built-in Self-Test and Built-in Self-Repair Strategies Without Golden Signature for Computing in Memory., , , , and . DATE, page 1-6. IEEE, (2023)A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning., , , , , , , , , and 6 other author(s). ISSCC, page 396-398. IEEE, (2019)