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Disambiguation of "Lee, Daeyeal"

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A 64Gb 533Mb/s DDR interface MLC NAND Flash in sub-20nm technology.

, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , and . ISSCC, page 430-432. IEEE, (2012)

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Xavier Lee Lee

Bongsoo Lee

The role of negative regulators in coordination of the Myxococcus xanthus developmental program. Uni Marburg, (2009)

Min-Hi Lee

Induction and regulation of antiviral defence mechanisms through intracytoplasmic sensors. HU Berlin, (2009)

Viktor Lee

Hyemin Lee

 

Other publications of authors with the same name

SMT-Based Contention-Free Task Mapping and Scheduling on SMART NoC., , and . IEEE Embed. Syst. Lett., 13 (4): 158-161 (2021)A Routability-Driven Complimentary-FET (CFET) Standard Cell Synthesis Framework using SMT., , , and . ICCAD, page 158:1-158:8. IEEE, (2020)CoRe-ECO: Concurrent Refinement of Detailed Place-and-Route for an Efficient ECO Automation., , , , , , , and . ICCD, page 366-373. IEEE, (2021)Logical Reasoning Techniques for VLSI Applications. University of California, San Diego, USA, (2022)SP&R: Simultaneous Placement and Routing framework for standard cell synthesis in sub-7nm., , , , , and . ASP-DAC, page 345-350. IEEE, (2020)A 64Gb 533Mb/s DDR interface MLC NAND Flash in sub-20nm technology., , , , , , , , , and 27 other author(s). ISSCC, page 430-432. IEEE, (2012)Complementary-FET (CFET) Standard Cell Synthesis Framework for Design and System Technology Co-Optimization Using SMT., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 29 (6): 1178-1191 (2021)SMT-Based Contention-Free Task Mapping and Scheduling on 2D/3D SMART NoC with Mixed Dimension-Order Routing., , and . ACM Trans. Archit. Code Optim., 19 (1): 5:1-5:21 (2022)Standard-Cell Scaling Framework with Guaranteed Pin-Accessibility., , and . ISCAS, page 1-5. IEEE, (2020)An Effective Test Pattern Generation for Testing Signal Integrity., , , , and . ATS, page 279-286. IEEE, (2006)