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THUEE System for NIST SRE19 CTS Challenge.

R. Li, T. Liang, D. Song, Y. Liu, Y. Wu, C. Xu, P. Ouyang, X. Zhang, X. Chen, W. Zhang, S. Yin, and L. He. INTERSPEECH, page 2232-2236. ISCA, (2020)

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Shouyi Zhang

Li Yin

Zhihong Yin

Lu Yin

Other publications of authors with the same name

A high efficient baseband transceiver for IEEE 802.15.4 LR-WPAN systems.S. Yin, J. Cui, A. Luo, L. Liu, and S. Wei. ASICON, page 224-227. IEEE, (2011)An Ultra-High Energy-Efficient Reconfigurable Processor for Deep Neural Networks with Binary/Ternary Weights in 28NM CMOS.S. Yin, P. Ouyang, J. Yang, T. Lu, X. Li, L. Liu, and S. Wei. VLSI Circuits, page 37-38. IEEE, (2018)A Novel Composite Method to Accelerate Control Flow on Reconfigurable Architecture (Abstract Only).J. Wang, L. Liu, J. Zhu, S. Yin, and S. Wei. FPGA, page 270. ACM, (2015)Anole: A Highly Efficient Dynamically Reconfigurable Crypto-Processor for Symmetric-Key Algorithms.L. Liu, B. Wang, C. Deng, M. Zhu, S. Yin, and S. Wei. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (12): 3081-3094 (2018)Data-Flow Graph Mapping Optimization for CGRA With Deep Reinforcement Learning.D. Liu, S. Yin, G. Luo, J. Shang, L. Liu, S. Wei, Y. Feng, and S. Zhou. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (12): 2271-2283 (2019)Sandwich-RAM: An Energy-Efficient In-Memory BWN Architecture with Pulse-Width Modulation.J. Yang, Y. Kong, Z. Wang, Y. Liu, B. Wang, S. Yin, and L. Shi. ISSCC, page 394-396. IEEE, (2019)A Multiple-Precision Multiply and Accumulation Design with Multiply-Add Merged Strategy for AI Accelerating.S. Zhang, J. Gu, S. Yin, L. Liu, and S. Wei. ASP-DAC, page 229-234. ACM, (2021)ReDCIM: Reconfigurable Digital Computing- In -Memory Processor With Unified FP/INT Pipeline for Cloud AI Acceleration.F. Tu, Y. Wang, Z. Wu, L. Liang, Y. Ding, B. Kim, L. Liu, S. Wei, Y. Xie, and S. Yin. IEEE J. Solid State Circuits, 58 (1): 243-255 (2023)Near-Optimal MIMO-SCMA Uplink Detection With Low-Complexity Expectation Propagation.P. Wang, L. Liu, S. Zhou, G. Peng, S. Yin, and S. Wei. IEEE Trans. Wirel. Commun., 19 (2): 1025-1037 (2020)SDP: Co-Designing Algorithm, Dataflow, and Architecture for In-SRAM Sparse NN Acceleration.F. Tu, Y. Wang, L. Liang, Y. Ding, L. Liu, S. Wei, S. Yin, and Y. Xie. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (1): 109-121 (2023)

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Disambiguation of "Yin, Shouyi"

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THUEE System for NIST SRE19 CTS Challenge.

Please choose a person to relate this publication to

Shouyi Zhang

Shouyi Zhang

Li Yin

Zhihong Yin

Lu Yin

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Yin, Shouyi"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML THUEE System for NIST SRE19 CTS Challenge.

Please choose a person to relate this publication to

Shouyi Zhang

Shouyi Zhang

Li Yin

Zhihong Yin

Lu Yin

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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URL
DOI
BibTeX
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APA
Chicago
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THUEE System for NIST SRE19 CTS Challenge.