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A high efficient baseband transceiver for IEEE 802.15.4 LR-WPAN systems., , , , and . ASICON, page 224-227. IEEE, (2011)An Ultra-High Energy-Efficient Reconfigurable Processor for Deep Neural Networks with Binary/Ternary Weights in 28NM CMOS., , , , , , and . VLSI Circuits, page 37-38. IEEE, (2018)A Novel Composite Method to Accelerate Control Flow on Reconfigurable Architecture (Abstract Only)., , , , and . FPGA, page 270. ACM, (2015)Anole: A Highly Efficient Dynamically Reconfigurable Crypto-Processor for Symmetric-Key Algorithms., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (12): 3081-3094 (2018)Data-Flow Graph Mapping Optimization for CGRA With Deep Reinforcement Learning., , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (12): 2271-2283 (2019)Sandwich-RAM: An Energy-Efficient In-Memory BWN Architecture with Pulse-Width Modulation., , , , , , and . ISSCC, page 394-396. IEEE, (2019)A Multiple-Precision Multiply and Accumulation Design with Multiply-Add Merged Strategy for AI Accelerating., , , , and . ASP-DAC, page 229-234. ACM, (2021)ReDCIM: Reconfigurable Digital Computing- In -Memory Processor With Unified FP/INT Pipeline for Cloud AI Acceleration., , , , , , , , , and . IEEE J. Solid State Circuits, 58 (1): 243-255 (2023)Near-Optimal MIMO-SCMA Uplink Detection With Low-Complexity Expectation Propagation., , , , , and . IEEE Trans. Wirel. Commun., 19 (2): 1025-1037 (2020)SDP: Co-Designing Algorithm, Dataflow, and Architecture for In-SRAM Sparse NN Acceleration., , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (1): 109-121 (2023)