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Disambiguation of "Hsieh, Chih-Cheng"

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A 0.4V 2.02fJ/conversion-step 10-bit hybrid SAR ADC with time-domain quantizer in 90nm CMOS.

, and . VLSIC, page 1-2. IEEE, (2014)

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Chih-Peng Hsieh

Chih-sheng Hsieh

Chih-Jen Hsieh

Chih-Cheng Jeng

Chih-Hong Cheng

 

Other publications of authors with the same name

An 8-bit column-shared SAR ADC for CMOS image sensor applications., , , , , , , , and . ISCAS, page 301-304. IEEE, (2015)A dual-mode CMOS image sensor for optical wireless communication., , , and . VLSI-DAT, page 1-4. IEEE, (2014)A 1V 14kfps smart CMOS imager with tracking and edge-detection modes for biomedical monitoring., and . VLSI-DAT, page 1-4. IEEE, (2013)A 0.5 V 12-bit SAR ADC using adaptive timedomain comparator with noise optimization., , and . A-SSCC, page 213-216. IEEE, (2017)8-b Precision 8-Mb ReRAM Compute-in-Memory Macro Using Direct-Current-Free Time-Domain Readout Scheme for AI Edge Devices., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 58 (1): 303-315 (2023)A hybrid CMOS-imager with perovskites as photoactive layer., , , , , , , and . IEEE SENSORS, page 1-3. IEEE, (2016)A new CMOS image sensor readout structure for 3D integrated imagers., , , , and . CICC, page 1-4. IEEE, (2011)15.4 A 22nm 2Mb ReRAM Compute-in-Memory Macro with 121-28TOPS/W for Multibit MAC Computing for Tiny AI Edge Devices., , , , , , , , , and 10 other author(s). ISSCC, page 244-246. IEEE, (2020)Session 27 Overview: Discrete-Time ADCs Data Converters Subcommittee., , and . ISSCC, page 368-369. IEEE, (2021)A 22nm 4Mb 8b-Precision ReRAM Computing-in-Memory Macro with 11.91 to 195.7TOPS/W for Tiny AI Edge Devices., , , , , , , , , and 8 other author(s). ISSCC, page 245-247. IEEE, (2021)