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COPPTCHA: COPPA Tracking by Checking Hardware-Level Activity.

, , , and . IEEE Trans. Inf. Forensics Secur., (2020)

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A Technique for Electrical Error Localization with Learning Methods During Post-silicon Debugging., , and . IGSC, page 1-8. IEEE, (2018)Black-Hat High-Level Synthesis: Myth or Reality?, , , and . IEEE Trans. Very Large Scale Integr. Syst., 27 (4): 913-926 (2019)Improving post-silicon error detection with topological selection of trace signals., , , , and . VLSI-SoC, page 1-6. IEEE, (2017)Exploring Fault-Energy Trade-offs in Approximate DNN Hardware Accelerators., , and . ISQED, page 343-348. IEEE, (2021)Can Overclocking Detect Hardware Trojans?, , , and . ISCAS, page 1-5. IEEE, (2021)RIBoNN: Designing Robust In-Memory Binary Neural Network Accelerators., , , , and . ITC, page 504-508. IEEE, (2022)ELURA: A Methodology for Post-Silicon Gate-Level Error Localization Using Regression Analysis., , , and . VLSID, page 410-415. IEEE Computer Society, (2018)Efficient Post-Silicon Validation of Network-on-Chip Using Wireless Links., , and . VLSID, page 371-376. IEEE, (2019)Efficient Trace Signal Selection for Post Silicon Validation and Debug., and . VLSI Design, page 352-357. IEEE Computer Society, (2011)PREEMPT: PReempting Malware by Examining Embedded Processor Traces., , , and . DAC, page 166. ACM, (2019)