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A Method of Generating Tests for Marginal Delays an Delay Faults in Combinational Circuits.

, , , and . Asian Test Symposium, page 320-325. IEEE Computer Society, (1997)

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On the fault diagnosis in the presence of unknown fault models using pass/fail information., , , , and . ISCAS (3), page 2987-2990. IEEE, (2005)Compaction of pass/fail-based diagnostic test vectors for combinational and sequential circuits., , , , and . ASP-DAC, page 659-664. IEEE, (2006)Test research in Japan., , , , , and . IEEE Des. Test, 5 (5): 60-79 (1988)Simulation-Based Diagnosis for Crosstalk Faults in Sequential Circuits., , , , and . Asian Test Symposium, page 63-. IEEE Computer Society, (2001)Enhancing BIST Based Single/Multiple Stuck-at Fault Diagnosis by Ambiguous Test Set., , , and . Asian Test Symposium, page 216-221. IEEE Computer Society, (2004)Multiple Fault Diagnosis in Logic Circuits Using EB Tester and Multiple/Single Fault Simulators., , , and . Asian Test Symposium, page 341-346. IEEE Computer Society, (1999)Test generation for scan design circuits with tri-state modules and bidirectional terminals., , , , and . DAC, page 71-78. ACM/IEEE, (1983)Reduction of Target Fault List for Crosstalk-Induced Delay Faults by using Layout Constraints., , , , and . Asian Test Symposium, page 242-247. IEEE Computer Society, (2002)A New Method for Diagnosing Multiple Stuck-at Faults using Multiple and Single Fault Simulations., , and . VTS, page 64-69. IEEE Computer Society, (1999)An Alternative Method of Generating Tests for Path Delay Faults Using N -Detection Test Sets., , and . PRDC, page 275-282. IEEE Computer Society, (2002)