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RMP-MEM: A HW/SW Reconfigurable Multi-Port Memory Architecture for Multi-PEA Oriented CGRA.

, , , , , , , , и . DAC, стр. 1-6. IEEE, (2023)

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Shaojun Lu

Shaojun Tong

Wei Wei

Wei Wei

Wei Wei

 

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Affine transformations for communication and reconfiguration optimization of loops on CGRAs., , , и . ISCAS, стр. 2541-2544. IEEE, (2013)Reconfigurable computing - evolution of Von Neumann architecture.. FPT, IEEE, (2010)A Coarse-Grained Reconfigurable Architecture for Compute-Intensive MapReduce Acceleration., , , , и . Computer Architecture Letters, 15 (2): 69-72 (2016)Memory fartitioning-based modulo scheduling for high-level synthesis., , , , , и . ISCAS, стр. 1-4. IEEE, (2017)Data cache prefetching via context directed pattern matching for coarse-grained reconfigurable arrays., , , и . DAC, стр. 64:1-64:6. ACM, (2016)Aggressive Pipelining of Irregular Applications on Reconfigurable Hardware., , , , , и . ISCA, стр. 575-586. ACM, (2017)A 2.69 Mbps/mW 1.09 Mbps/kGE Conjugate Gradient-based MMSE Detector for 64-QAM 128×8 Massive MIMO Systems., , , , , и . A-SSCC, стр. 191-194. IEEE, (2018)LCP: a layer clusters paralleling mapping method for accelerating inception and residual networks on FPGA., , , , , и . DAC, стр. 16:1-16:6. ACM, (2018)An efficient kernel transformation architecture for binary- and ternary-weight neural network inference., , , , и . DAC, стр. 137:1-137:6. ACM, (2018)Polyhedral model based mapping optimization of loop nests for CGRAs., , , и . DAC, стр. 19:1-19:8. ACM, (2013)