Author of the publication

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

An efficient kernel transformation architecture for binary- and ternary-weight neural network inference.

S. Zheng, Y. Liu, S. Yin, L. Liu, and S. Wei. DAC, page 137:1-137:6. ACM, (2018)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Shaojun Lu

Shaojun Tong

Wei Wei

Other publications of authors with the same name

Affine transformations for communication and reconfiguration optimization of loops on CGRAs.D. Liu, S. Yin, L. Liu, and S. Wei. ISCAS, page 2541-2544. IEEE, (2013)Memory fartitioning-based modulo scheduling for high-level synthesis.T. Lu, S. Yin, X. Yao, Z. Xie, L. Liu, and S. Wei. ISCAS, page 1-4. IEEE, (2017)A Coarse-Grained Reconfigurable Architecture for Compute-Intensive MapReduce Acceleration.S. Liang, S. Yin, L. Liu, Y. Guo, and S. Wei. Computer Architecture Letters, 15 (2): 69-72 (2016)Reconfigurable computing - evolution of Von Neumann architecture.S. Wei. FPT, IEEE, (2010)Data cache prefetching via context directed pattern matching for coarse-grained reconfigurable arrays.C. Yang, L. Liu, S. Yin, and S. Wei. DAC, page 64:1-64:6. ACM, (2016)A 2.69 Mbps/mW 1.09 Mbps/kGE Conjugate Gradient-based MMSE Detector for 64-QAM 128×8 Massive MIMO Systems.G. Peng, L. Liu, Q. Wei, Y. Wang, S. Yin, and S. Wei. A-SSCC, page 191-194. IEEE, (2018)Aggressive Pipelining of Irregular Applications on Reconfigurable Hardware.Z. Li, L. Liu, Y. Deng, S. Yin, Y. Wang, and S. Wei. ISCA, page 575-586. ACM, (2017)AEPE: An area and power efficient RRAM crossbar-based accelerator for deep CNNs.S. Tang, S. Yin, S. Zheng, P. Ouyang, F. Tu, L. Yao, J. Wu, W. Cheng, L. Liu, and S. Wei. NVMSA, page 1-6. IEEE, (2017)Energy-aware loops mapping on multi-vdd CGRAs without performance degradation.J. Gu, S. Yin, L. Liu, and S. Wei. ASP-DAC, page 312-317. IEEE, (2017)Polyhedral model based mapping optimization of loop nests for CGRAs.D. Liu, S. Yin, L. Liu, and S. Wei. DAC, page 19:1-19:8. ACM, (2013)

BibSonomy

Disambiguation of "Wei, Shaojun"

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

An efficient kernel transformation architecture for binary- and ternary-weight neural network inference.

Please choose a person to relate this publication to

Shaojun Lu

Shaojun Tong

Wei Wei

Wei Wei

Wei Wei

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Wei, Shaojun"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML An efficient kernel transformation architecture for binary- and ternary-weight neural network inference.

Please choose a person to relate this publication to

Shaojun Lu

Shaojun Tong

Wei Wei

Wei Wei

Wei Wei

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

An efficient kernel transformation architecture for binary- and ternary-weight neural network inference.