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Disambiguation of "Iizuka, Tetsuya"

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A Charge-Redistribution Multi-Bit Stochastic-Resonance ADC Enhancing SNDR for Weak Input Signal.

, , , , and . ISCAS, page 3224-3228. IEEE, (2022)

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Tetsuya Takahashi

Hajime Iizuka

Tetsuya Mizutani

Tetsuya Kawata

Tetsuya Takahashi

 

Other publications of authors with the same name

A calibration-free time difference accumulator using two pulses propagating on a single buffer ring., , , and . A-SSCC, page 1-4. IEEE, (2015)Automatic Visualization Method for Visual Data Mining., , , and . PAKDD, volume 1394 of Lecture Notes in Computer Science, page 173-185. Springer, (1998)A high frequency resolution Digitally-Controlled Oscillator using single-period switching scheme., , and . ESSCIRC, page 399-402. IEEE, (2011)A true 4-cycle lock reference-less all-digital burst-mode CDR utilizing coarse-fine phase generator with embedded TDC., , , , and . CICC, page 1-4. IEEE, (2013)7.5Vmax arbitrary waveform generator with 65nm standard CMOS under 1.2V supply voltage., , , and . CICC, page 1-4. IEEE, (2012)Embedded tutorial: Test and manufacturability for silicon photonics and 3D integration., and . CICC, page 1. IEEE, (2014)An ultra-wide-range fine-resolution two-step time-to-digital converter with built-in foreground coarse gain calibration., , , and . ICECS, page 231-234. IEEE, (2017)A triangular active charge injection scheme using a resistive current for resonant power supply noise suppression., , , and . ICECS, page 318-321. IEEE, (2017)A 65 nm CMOS Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion with 99.6% Current Efficiency at 10-mA Load., , , and . VLSI-SoC (Selected Papers), volume 561 of IFIP Advances in Information and Communication Technology, page 1-13. Springer, (2018)A 0.0053-mm2 6-bit Fully-Standard-Cell-Based Synthesizable SAR ADC in 65 nm CMOS., , and . NEWCAS, page 1-4. IEEE, (2019)