( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
Accelerating Convolutional Neural Networks by Exploiting the Sparsity of Output Activation.

, , , , , , , , , , , и . IEEE Trans. Parallel Distributed Syst., 34 (12): 3253-3265 (декабря 2023)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Dongrui Deng

Fan Dai

Min Fan

Xiaohua Fan

Hua Fan

 

Другие публикации лиц с тем же именем

Hardware Acceleration for GCNs via Bidirectional Fusion., , , , , , , и . IEEE Comput. Archit. Lett., 20 (1): 66-69 (2021)Optimized Register Renaming Scheme for Stack-Based x86 Operations., , , , , , , , и . ARCS, том 4415 из Lecture Notes in Computer Science, стр. 43-56. Springer, (2007)Self-Correction Trace Model: A Full-System Simulator for Optical Network-on-Chip., , и . IPDPS Workshops, стр. 242-247. IEEE Computer Society, (2012)Performance analysis and optimization of molecular dynamics simulation on Godson-T many-core processor., , , , , , , и . Conf. Computing Frontiers, стр. 32. ACM, (2011)An Evolutionary Technique for Performance-Energy-Temperature Optimized Scheduling of Parallel Tasks on Multi-Core Processors., , и . IEEE Trans. Parallel Distributed Syst., 27 (3): 668-681 (2016)Scalable and efficient graph traversal on high-throughput cluster., , , , , и . CCF Trans. High Perform. Comput., 3 (1): 101-113 (2021)Rethinking Efficiency and Redundancy in Training Large-scale Graphs., , , , , , и . CoRR, (2022)Enabling coordinated register allocation and thread-level parallelism optimization for GPUs., , , , , , и . MICRO, стр. 395-406. ACM, (2015)Minimal Multi-threading: Finding and Removing Redundant Instructions in Multi-threaded Processors., , , , , , и . MICRO, стр. 337-348. IEEE Computer Society, (2010)A Loop Optimization Method for Dataflow Architecture., , , , , , , и . HPCC/DSS/SmartCity/DependSys, стр. 202-211. IEEE, (2022)