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DVFS-Based Scrubbing Scheduling for Reliability Maximization on Parallel Tasks in SRAM-based FPGAs.

, , , и . DAC, стр. 1-6. IEEE, (2020)

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Yajun Fang

Yajun Xiao

Yajun Cheng

Hoang Ha

Ngo Ha

 

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Building a Virtual Framework for Networked Reconfigurable Hardware and Software Objects., , , , и . PDPTA, CSREA Press, (2000)Power-aware FPGA technology mapping for programmable-VT architectures (abstract only)., и . FPGA, стр. 268. ACM, (2012)An automated, efficient and static bit-width optimization methodology towards maximum bit-width-to-error tradeoff with affine arithmetic model., и . ASP-DAC, стр. 886-891. IEEE, (2006)Fast and Accurate Interval-Based Timing Estimator for Variability-Aware FPGA Physical Synthesis Tools., , , и . FPL, стр. 279-284. IEEE, (2007)ParaFRo: A hybrid parallel FPGA router using fine grained synchronization and partitioning., , и . FPL, стр. 1-11. IEEE, (2016)Optimization of FPGA Routing Networks with Time-Multiplexed Interconnects., , и . LASCAS, стр. 1-4. IEEE, (2020)Analysis and Design of Reconfigurable Sense Amplifier for Compute SRAM With High-Speed Compute and Normal Read Access., , , и . IEEE Trans. Circuits Syst. II Express Briefs, 68 (12): 3503-3507 (2021)Generalized Hyperbolic CORDIC and Its Logarithmic and Exponential Computation With Arbitrary Fixed Base., , , , , и . IEEE Trans. Very Large Scale Integr. Syst., 27 (9): 2156-2169 (2019)Cryogenic quasi-static embedded DRAM for energy-efficient compute-in-memory applications., , , , , , , , , и 2 other автор(ы). CoRR, (2023)HRFF: Hierarchical and Recursive Floorplanning Framework for NoC-Based Scalable Multidie FPGAs., , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 70 (11): 4295-4308 (ноября 2023)