Author of the publication

A method of hidden faults opposition for FPGA-based components of safety-related systems.

, , , , and . CMIS, volume 2608 of CEUR Workshop Proceedings, page 311-322. CEUR-WS.org, (2020)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A method of hidden faults opposition for FPGA-based components of safety-related systems., , , , and . CMIS, volume 2608 of CEUR Workshop Proceedings, page 311-322. CEUR-WS.org, (2020)Use of Natural LUT Redundancy to Improve Trustworthiness of FPGA Design., , and . ICTERI, volume 1614 of CEUR Workshop Proceedings, page 322-331. CEUR-WS.org, (2016)A Method to Improve FPGA Project Checkability for Safety-Related Applications., , , , , and . ICST, volume 2711 of CEUR Workshop Proceedings, page 150-160. CEUR-WS.org, (2020)An Approach to Stego-Container Organization in FPGA Systems for Approximate Data Processing., , , , and . IntelITSIS, volume 2853 of CEUR Workshop Proceedings, page 527-536. CEUR-WS.org, (2021)Empirical Investigation of Offloading Decision Making in Industrial Edge Computing Scenarios., , , , and . EuCNC/6G Summit, page 311-316. IEEE, (2021)Recovering From a Failure and Improving the Checkability of Iterative Array Dividers., , , , , , , , and . CSIT, page 523-526. IEEE, (2022)Use of Natural Information Redundancy in On-Line Testing of Computer Systems and their Components., , , , and . EWDTS, page 1-5. IEEE, (2019)Evolution of a Problem of the Hidden Faults in the Digital Components of Safety-Related Systens., , , , , and . EWDTS, page 1-5. IEEE, (2018)Improving of a Circuit Checkability and Trustworthiness of Data Processing Results in LUT-based FPGA Components of Safety-Related Systems., , , and . ICTERI, volume 1844 of CEUR Workshop Proceedings, page 654-661. CEUR-WS.org, (2017)Using Natural Version Redundancy of FPGA Projects in Area of Critical Applications., , , , and . DESSERT, page 58-64. IEEE, (2020)