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A method of hidden faults opposition for FPGA-based components of safety-related systems., , , , и . CMIS, том 2608 из CEUR Workshop Proceedings, стр. 311-322. CEUR-WS.org, (2020)Use of Natural LUT Redundancy to Improve Trustworthiness of FPGA Design., , и . ICTERI, том 1614 из CEUR Workshop Proceedings, стр. 322-331. CEUR-WS.org, (2016)Power-Oriented Checkability of Matrix and Pipeline Circuits in FPGA-Based Digital Components of Safety-Related Systems., , , и . ICTERI Workshops, том 2393 из CEUR Workshop Proceedings, стр. 749-761. CEUR-WS.org, (2019)Sharing of Functional and Special Means in Pipeline Floating-Point Systems with Strongly Connected Versions., , , , и . IDAACS, стр. 249-253. IEEE, (2019)Models and methods checking mantissas by inequalities for on-line testing of digital circuits in critical applications., , , , и . EWDTS, стр. 1-5. IEEE Computer Society, (2017)A Method of Common Signal Monitoring in FPGA-Based Components of Safety-Related Systems., , , и . CMIS, том 2353 из CEUR Workshop Proceedings, стр. 924-934. CEUR-WS.org, (2019)Improving of a Circuit Checkability and Trustworthiness of Data Processing Results in LUT-based FPGA Components of Safety-Related Systems., , , и . ICTERI, том 1844 из CEUR Workshop Proceedings, стр. 654-661. CEUR-WS.org, (2017)Features of Hidden Fault Detection in Pipeline Digital Components of Safety-Related Systems., , и . ICTERI, том 1356 из CEUR Workshop Proceedings, стр. 476-485. CEUR-WS.org, (2015)Evolution of a Problem of the Hidden Faults in the Digital Components of Safety-Related Systens., , , , , и . EWDTS, стр. 1-5. IEEE, (2018)Checkability of the digital components in safety-critical systems: Problems and solutions., , , , и . EWDTS, стр. 411-416. IEEE Computer Society, (2011)