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Buck-boost switched-capacitor DC-DC voltage regulator using delta-sigma control loop.

, , , , and . ISCAS (4), page 743-746. IEEE, (2002)

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Design of a 79 dB 80 MHz 8X-OSR Hybrid Delta-Sigma/Pipelined ADC., , , , , , and . IEEE J. Solid State Circuits, 45 (4): 719-730 (2010)A +5dBFS third-order extended dynamic range single-loop ΔΣ modulator., , and . CICC, page 1-4. IEEE, (2010)A 2.5-V 10-b 120-MSample/s CMOS pipelined ADC based on merged-capacitor switching., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 51-II (5): 269-275 (2004)Continuous-time filter design optimized for reduced die area., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 51-II (3): 105-110 (2004)Domino-Logic-Based ADC for Digital Synthesis., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 58-II (11): 744-747 (2011)An extended radix-based digital calibration technique for multi-stage ADC., and . ISCAS (1), page 829-832. IEEE, (2003)Low-distortion delta-sigma topologies for MASH architectures., , and . ISCAS (1), page 1144-1147. IEEE, (2004)Jitter in high-speed serial and parallel links., , , , and . ISCAS (4), page 425-428. IEEE, (2004)Parameter variation analysis for voltage controlled oscillators in phase-locked loops., , , and . ISCAS, page 716-719. IEEE, (2008)Enhanced multi-bit delta-sigma modulator with two-step pipeline quantizer., and . ISCAS, page 1212-1215. IEEE, (2008)