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FeFET based Logic-in-Memory: an overview.

, , , , , и . DTIS, стр. 1-6. IEEE, (2021)

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Cédric Müller

Cédric Bodet

Cédric Allène

Cédric Joffroy

Cédric Penet

 

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Conflict Resolution by Matrix Reordering for DVB-T2 LDPC Decoders., , , и . GLOBECOM, стр. 1-6. IEEE, (2009)Conflict resolution for pipelined layered LDPC decoders., , , и . SiPS, стр. 220-225. IEEE, (2009)Design and Characterization of the TERO-PUF on SRAM FPGAs., , и . ISVLSI, стр. 134-139. IEEE Computer Society, (2016)Prospects for energy-efficient edge computing with integrated HfO2-based ferroelectric devices., , , , , , , , , и 2 other автор(ы). VLSI-SoC, стр. 180-183. IEEE, (2018)NB-LDPC check node with pre-sorted input., и . ISTC, стр. 196-200. IEEE, (2016)FeFET based Logic-in-Memory design methodologies, tools and open challenges., , , , , и . VLSI-SoC, стр. 1-6. IEEE, (2023)Hardware Discrete Channel Emulator., , , и . HPCS, стр. 452-458. IEEE, (2010)Non Volatile Operators Emulation Platform., , и . NANOARCH, стр. 15:1-15:6. ACM, (2023)Hardware Emulation of FeFET On FPGA., , , и . ISVLSI, стр. 380-385. IEEE, (2022)Energy-efficient Computation-In-Memory Architecture using Emerging Technologies., , , , , , , , , и 2 other автор(ы). ICM, стр. 325-334. IEEE, (2023)