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Low-Cost Inter-Linked Subarrays (LISA): Enabling fast inter-subarray data movement in DRAM.

, , , , , and . HPCA, page 568-580. IEEE Computer Society, (2016)

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Reducing DRAM Latency by Exploiting Design-Induced Latency Variation in Modern DRAM Chips., , , , , , , and . CoRR, (2016)Improving Multi-Application Concurrency Support Within the GPU Memory System., , , , , , , and . CoRR, (2017)Accelerating Neural Network Inference with Processing-in-DRAM: From the Edge to the Cloud., , , , and . CoRR, (2022)Heterogeneous Data-Centric Architectures for Modern Data-Intensive Applications: Case Studies in Machine Learning and Databases., , , , and . ISVLSI, page 273-278. IEEE, (2022)Low-Cost Inter-Linked Subarrays (LISA): Enabling fast inter-subarray data movement in DRAM., , , , , and . HPCA, page 568-580. IEEE Computer Society, (2016)Utility-Based Hybrid Memory Management., , , , , and . CLUSTER, page 152-165. IEEE Computer Society, (2017)Carpool: a bufferless on-chip network supporting adaptive multicast and hotspot alleviation., , , , , and . ICS, page 19:1-19:11. ACM, (2017)Google Workloads for Consumer Devices: Mitigating Data Movement Bottlenecks., , , , , , , , , and 1 other author(s). ASPLOS, page 316-331. ACM, (2018)FIGARO: Improving System Performance via Fine-Grained In-DRAM Data Relocation and Caching., , , , , , , , , and 1 other author(s). MICRO, page 313-328. IEEE, (2020)SIMDRAM: An End-to-End Framework for Bit-Serial SIMD Computing in DRAM., , , , , , , , , and . CoRR, (2021)