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Performance-driven mapping for CPLD architectures., , , and . FPGA, page 39-47. ACM, (2001)Debugging and verifying SoC designs through effective cross-layer hardware-software co-simulation., , , , , and . DAC, page 7:1-7:6. ACM, (2016)Resource and data optimization for hardware implementation of deep neural networks targeting FPGA-based edge devices., , , and . SLIP@DAC, page 1:1-1:8. ACM, (2018)Optimality study of resource binding with multi-Vdds., , , and . DAC, page 580-585. ACM, (2006)Throughput-oriented kernel porting onto FPGAs., , , , and . DAC, page 11:1-11:10. ACM, (2013)ScaleHLS: A New Scalable High-Level Synthesis Framework on Multi-Level Intermediate Representation., , , , , , and . HPCA, page 741-755. IEEE, (2022)FSSD: FPGA-Based Emulator for SSDs., , , , , , , and . FPL, page 101-108. IEEE, (2023)Is FPGA Useful for Hash Joins?, , , , , , and . CIDR, www.cidrdb.org, (2020)High-level synthesis with behavioral level multi-cycle path analysis., , , , and . FPL, page 1-8. IEEE, (2013)A SPICE-compatible model of graphene nano-ribbon field-effect transistors enabling circuit-level delay and power analysis under process variation., , , , , and . DATE, page 1789-1794. EDA Consortium San Jose, CA, USA / ACM DL, (2013)