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Disambiguation of "Hariyama, Masanori"

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A Multi-Context FPGA Using a Floating-Gate-MOS Functional Pass-Gate and Its CAD Environment.

, and . APCCAS, page 1803-1806. IEEE, (2006)

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Other publications of authors with the same name

Non-Volatile Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals., , , and . ERSA, page 309-310. CSREA Press, (2008)Benchmarks for FPGA-Targeted High-Level-Synthesis., , and . CANDAR, page 232-238. IEEE, (2019)Hardware-oriented succinct-data-structure based on block-size-constrained compression., , and . SoCPaR, page 136-140. IEEE, (2015)Implementation of an FPGA-Oriented Complex Number Computation Library Using Intel OneAPI DPC++., , and . MWSCAS, page 1-4. IEEE, (2022)Low-Power Field-Programmable VLSI Processor Using Dynamic Circuits., , and . ISVLSI, page 243-248. IEEE Computer Society, (2004)Switch Block Architecture for Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals., , and . ISMVL, page 17. IEEE Computer Society, (2006)Architecture of an FPGA accelerator for molecular dynamics simulation using OpenCL., , and . ICIS, page 1-5. IEEE Computer Society, (2016)FPGA-Based Acceleration of Word2vec using OpenCL., , , , , , and . ISCAS, page 1-5. IEEE, (2019)Evaluation of an FPGA-Based Heterogeneous Multicore Platform with SIMD/MIMD Custom Accelerators., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 96-A (12): 2576-2586 (2013)Genetic Approach to Minimizing Energy Consumption of VLSI Processors Using Multiple Supply Voltages., , and . IEEE Trans. Computers, 54 (6): 642-650 (2005)