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A Methodology for Automated Verification of Synthesized RTL Designs and Its Integration with a High-Level Synthesis Tool., и . FMCAD, том 1522 из Lecture Notes in Computer Science, стр. 204-221. Springer, (1998)An ILP Formulation for Task Scheduling on Heterogeneous Chip Multiprocessors., , , и . ISCIS, том 4263 из Lecture Notes in Computer Science, стр. 267-276. Springer, (2006)Determining the Optimal Number of Islands in Power Islands Synthesis., и . ISVLSI, стр. 22-27. IEEE Computer Society, (2008)Reliability-Centric Hardware/Software Co-Design., , , , , и . ISQED, стр. 375-380. IEEE Computer Society, (2005)Pre-Layout Estimation of Interconnect Lengths for Digital Integrated Circuits., , и . CONIELECOMP, стр. 38. IEEE Computer Society, (2006)Accounting for Various Register Allocation Schemes During Post-Synthesis Verification of RTL Designs., и . DATE, стр. 223-. IEEE Computer Society / ACM, (1999)Derving Intermediary RTLs for Verification of Pipelined Synthesized Designs., , и . VLSI, стр. 382-. CSREA Press, (2003)Exploiting PSL standard assertions in a theorem-proving-based verification environment., , и . ACM Great Lakes Symposium on VLSI, стр. 400-403. ACM, (2005)Power Islands: A High-Level Technique for Counteracting Leakage in Deep Sub-Micron., , и . ISQED, стр. 165-170. IEEE Computer Society, (2006)An ILP Formulation for Reliability-Oriented High-Level Synthesis., , , , , , и . ISQED, стр. 364-369. IEEE Computer Society, (2005)