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An OpenCL™ Deep Learning Accelerator on Arria 10.

, , , , и . FPGA, стр. 55-64. ACM, (2017)

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Davor Zavisic

Mark Davoren

Davor Turkovic

Davor Baros

Davor Zagorac

 

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Microarchitecture of a Coarse-Grain Out-of-Order Superscalar Processor., и . IEEE Trans. Parallel Distributed Syst., 24 (2): 392-405 (2013)Tile-based bottom-up compilation of custom mesh-of-functional-units FPGA overlays., и . FPL, стр. 1-8. IEEE, (2014)Customizable FPGA OpenCL matrix multiply design template for deep neural networks., , , , , , , и . FPT, стр. 259-262. IEEE, (2017)Flexibility: FPGAs and CAD in Deep Learning Acceleration., , , , и . ISPD, стр. 34-41. ACM, (2018)Compute Substrate for Software 2.0., , , , , , , , , и 34 other автор(ы). IEEE Micro, 41 (2): 50-55 (2021)In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC(Abstract Only)., , , , , , , , , и 1 other автор(ы). FPGA, стр. 287. ACM, (2018)An OpenCL™ Deep Learning Accelerator on Arria 10., , , , и . FPGA, стр. 55-64. ACM, (2017)Creating High Performance Applications with Intel's FPGA OpenCL™ SDK., , , , и . IWOCL, стр. 11:1. ACM, (2017)Towards Synthesis-Free JIT Compilation to Commodity FPGAs., и . FCCM, стр. 202-205. IEEE Computer Society, (2011)A high-performance overlay architecture for pipelined execution of data flow graphs., и . FPL, стр. 1-8. IEEE, (2013)