( en | de | ru )

 

Disambiguation of "Bitar, Andrew"

Author of the publication

copydeleteadd this publication to your clipboard
Flexibility: FPGAs and CAD in Deep Learning Acceleration.

, , , , and . ISPD, page 34-41. ACM, (2018)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Kamal Bitar

Djahanbakhsch Bitaraf

Mounir Bitar

Rima Bitar-Vollmer

Julia Bitar

 

Other publications of authors with the same name

Take the Highway: Design for Embedded NoCs on FPGAs., , and . FPGA, page 98-107. ACM, (2015)Harnessing Numerical Flexibility for Deep Learning on FPGAs., , , , , , , , , and 1 other author(s). HEART, page 1:1-1:3. ACM, (2018)DLA: Compiler and FPGA Overlay for Neural Network Inference Acceleration., , , , , , , , , and 1 other author(s). FPL, page 411-418. IEEE Computer Society, (2018)Efficient and programmable ethernet switching with a NoC-enhanced FPGA., , , and . ANCS, page 89-100. ACM, (2014)Bringing programmability to the data plane: Packet processing with a NoC-enhanced FPGA., , and . FPT, page 24-31. IEEE, (2015)Design and simulation tools for Embedded NOCs on FPGAs., , , and . FPL, page 1. IEEE, (2015)Design and Applications for Embedded Networks-on-Chip on FPGAs., , and . IEEE Trans. Computers, 66 (6): 1008-1021 (2017)Challenges/Opportunities to Enable Dependable Scale-out System with Groq Deterministic Tensor-Streaming Processors., , , , , , and . DSN (Supplements), page 19-22. IEEE, (2022)Flexibility: FPGAs and CAD in Deep Learning Acceleration., , , , and . ISPD, page 34-41. ACM, (2018)The Groq Software-defined Scale-out Tensor Streaming Multiprocessor : From chips-to-systems architectural overview., , , , , , , , , and . HCS, page 1-69. IEEE, (2022)