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A 2.6mW 6b 2.2GS/s 4-times interleaved fully dynamic pipelined ADC in 40nm digital CMOS., , , , и . ISSCC, стр. 296-297. IEEE, (2010)A low-complexity, low phase noise, low-voltage phase-aligned ring oscillator in 90 nm digital CMOS., , , , и . ESSCIRC, стр. 410-413. IEEE, (2008)Modeling of Substrate Noise Generation, Isolation, and Impact for an LC-VCO and a Digital Modem on a Lightly-Doped Substrate., , , , , , и . IEEE J. Solid State Circuits, 41 (9): 2040-2051 (2006)A Low-Complexity, Low-Phase-Noise, Low-Voltage Phase-Aligned Ring Oscillator in 90 nm Digital CMOS., , , , , и . IEEE J. Solid State Circuits, 44 (7): 1942-1949 (2009)21.4 A 42mW 230fs-jitter sub-sampling 60GHz PLL in 40nm CMOS., , , , , и . ISSCC, стр. 366-367. IEEE, (2014)Efficient Link Architecture for On-Chip Serial links and Networks., , , , , , и . SoC, стр. 1-4. IEEE, (2006)A 5 ps resolution, 8.6 ns delay range digital delay line using combinatorial redundancy., , , и . PRIME, стр. 21-24. IEEE, (2019)Correction: Jegannathan et al. An Overview of CMOS Photodetectors Utilizing Current-Assistance for Swift and Efficient Photo-Carrier Detection. Sensors 2021, 21, 4576., , , , , , и . Sensors, 22 (7): 2610 (2022)A switchable low-area 2.4-and-5 GHz dual-band LNA in digital CMOS., , , , и . ESSCIRC, стр. 376-379. IEEE, (2007)A power reduction method for off-chip interconnects., , , и . ISCAS, стр. 265-268. IEEE, (2000)