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Disambiguation of "Bhattacharya, Bhargab B."

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Reservoir and mixer constrained scheduling for sample preparation on digital microfluidic biochips.

, , , , , , and . ASP-DAC, page 702-707. IEEE, (2017)

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Chhaya Bhattacharya

Subhamoy Bhattacharya

Nupur Bhattacharya

Indrajit Bhattacharya

Asitesh Bhattacharya

 

Other publications of authors with the same name

Enumeration of Shortest Isothetic Paths Inside a Digital Object., , and . PReMI, volume 9124 of Lecture Notes in Computer Science, page 105-115. Springer, (2015)Determination of Minutiae Scores for Fingerprint Image Applications., , , , , and . ICVGIP, Allied Publishers Private Limited, (2002)Area(number)-balanced hierarchy of staircase channels with minimum crossing nets., , , and . ISCAS (5), page 395-398. IEEE, (2001)Isomorph-Redundancy in Sequential Circuits., , and . IEEE Trans. Computers, 49 (9): 992-997 (2000)A Methodology for Testing Arbitrary Bilateral Bit-Level Systolic Arrays., , and . VLSI Design, 4 (3): 257-269 (1996)Fast Estimation of Area-Coverage for Wireless Sensor Networks Based on Digital Geometry., , , and . IEEE Trans. Multi Scale Comput. Syst., 3 (3): 166-180 (2017)Test Generation for Flow-Based Microfluidic Biochips With General Architectures., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (10): 2530-2543 (2020)Via minimization in VLSI routing with movable terminals., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 8 (8): 917-920 (1989)Storage-Aware Algorithms for Dilution and Mixture Preparation With Flow-Based Lab-on-Chip., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (4): 816-829 (2020)Implementing Symmetric Functions with Hierarchical Modules for Stuck-At and Path-Delay Fault Testability., , and . J. Electron. Test., 22 (2): 125-142 (2006)