Author of the publication

Field Modifiable Architecture and its Design Methodology: System Design Without Logic Synthesis.

, , , , and . IWLS, page 103-108. (2002)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Object-oriented analysis and design of hardware/software co-designs with dependence analysis for design reuse., , and . IRI, page 318-325. IEEE Systems, Man, and Cybernetics Society, (2005)Global transaction ordering in Network-on-Chips for post-silicon validation., and . ISQED, page 284-289. IEEE, (2011)A small biped entertainment robot exploring attractive applications., , , , and . ICRA, page 471-476. IEEE, (2003)Tutorial: "Post silicon debug of SOC designs"., and . SoCC, page 18. IEEE, (2011)On variable ordering of binary decision diagrams for the application of multi-level logic synthesis., , and . EURO-DAC, page 50-54. EEE Computer Society, (1991)Automatic High-Level Data-Flow Synthesis and Optimization of Polynomial Datapaths Using Functional Decomposition., , , and . IEEE Trans. Computers, 64 (6): 1579-1593 (2015)RTL datapath optimization using system-level transformations., , , and . ISQED, page 309-316. IEEE, (2014)Specification and formal verification of power gating in processors., and . ISQED, page 604-610. IEEE, (2014)234 scheduling of 3-2 and 2-1 eliminations for parallel image compositing using non-power-of-two number of processes., , and . HPCS, page 421-428. IEEE, (2015)A new approach for selecting inputs of logic functions during debug., and . ISQED, page 166-173. IEEE, (2017)