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Decoupling the Multi-Rate Dataflow Execution in Coarse-Grained Reconfigurable Array.

T. Hong, N. Guan, C. Yin, Q. Wang, J. Jiang, J. Jin, G. He, and N. Jing. ISCAS, page 1-5. IEEE, (2020)

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Jianfei Kralle

Jianfei Wang

Jianfei Wei

Ping Jiang

Jiang Yi

Other publications of authors with the same name

Analog-to-digital converter based on single-electron tunneling transistors.C. Hu, S. Cotofana, J. Jiang, and Q. Cai. IEEE Trans. Very Large Scale Integr. Syst., 12 (11): 1209-1213 (2004)Decoupling the Multi-Rate Dataflow Execution in Coarse-Grained Reconfigurable Array.T. Hong, N. Guan, C. Yin, Q. Wang, J. Jiang, J. Jin, G. He, and N. Jing. ISCAS, page 1-5. IEEE, (2020)A CPU-FPGA Based Heterogeneous Accelerator for RepVGG.Y. Guo, M. Jiang, F. Dong, K. Yu, K. Chen, W. Qu, and J. Jiang. ASICON, page 1-4. IEEE, (2021)Design and Implementation of Flexible Dual-Mode Soft-Output MIMO Detector With Channel Preprocessing.Z. Yan, G. He, Y. Ren, W. He, J. Jiang, and Z. Mao. IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (11): 2706-2717 (2015)A Hierarchical Communication Algorithm for Distributed Deep Learning Training.J. Zhang, S. Cheng, F. Dong, K. Chen, Y. Qiao, Z. Mao, and J. Jiang. MWSCAS, page 526-530. IEEE, (2023)Reducing Memory Access Conflicts with Loop Transformation and Data Reuse on Coarse-grained Reconfigurable Architecture.Y. Chen, Z. Zhao, J. Jiang, G. He, Z. Mao, and W. Sheng. DATE, page 124-129. IEEE, (2021)Pipeline Balancing for Integrated Mapping in High Performance Spatial Programmable Architecture.P. Liu, Z. Zhang, C. Yin, L. Chen, J. Jiang, Q. Wang, Z. Mao, and N. Jing. FPL, page 116-122. IEEE, (2023)Design of a high voltage stimulator chip for a stroke rehabilitation system.L. Zeng, X. Yi, S. Lu, Y. Lou, J. Jiang, H. Qu, N. Lan, and G. Wang. EMBC, page 834-837. IEEE, (2013)Bridge-NDP: Achieving Efficient Communication-Computation Overlap in Near Data Processing with Bridge Architecture.L. Chen, J. Jiang, Q. Wang, Z. Mao, and N. Jing. ASPDAC, page 460-465. IEEE, (2024)Subgraph Decoupling and Rescheduling for Increased Utilization in CGRA Architecture.C. Yin, Q. Wang, J. Jiang, W. Sheng, G. He, Z. Mao, and N. Jing. DATE, page 1394-1399. IEEE, (2021)

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Disambiguation of "Jiang, Jianfei"

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Decoupling the Multi-Rate Dataflow Execution in Coarse-Grained Reconfigurable Array.

Please choose a person to relate this publication to

Jianfei Kralle

Jianfei Wang

Jianfei Wei

Ping Jiang

Jiang Yi

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Jiang, Jianfei"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Decoupling the Multi-Rate Dataflow Execution in Coarse-Grained Reconfigurable Array.

Please choose a person to relate this publication to

Jianfei Kralle

Jianfei Wang

Jianfei Wei

Ping Jiang

Jiang Yi

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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Decoupling the Multi-Rate Dataflow Execution in Coarse-Grained Reconfigurable Array.