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NimbleAI: Towards Neuromorphic Sensing-Processing 3D-integrated Chips.

, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , и . DATE, стр. 1-6. IEEE, (2023)

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Humberto Jorge José

Nadine José Gonzalez

José Baena

José Teixeira

José Izquierdo

 

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Fault-Tolerant Vertical Link Design for Effective 3D Stacking., , , , и . IEEE Comput. Archit. Lett., 10 (2): 41-44 (2011)Silicon-aware distributed switch architecture for on-chip networks., , , , и . J. Syst. Archit., 59 (7): 505-515 (2013)Network-on-Chip virtualization in Chip-Multiprocessor Systems., , , и . J. Syst. Archit., 58 (3-4): 126-139 (2012)Towards Efficient Neural Network Model Parallelism on Multi-FPGA Platforms., , и . DATE, стр. 1-6. IEEE, (2023)GEMM-Like Convolution for Deep Learning Inference on the Xilinx Versal., , , и . ISC Workshops, том 13999 из Lecture Notes in Computer Science, стр. 593-604. Springer, (2023)Understanding cache hierarchy interactions with a program-driven simulator., , , и . WCAE, стр. 30-35. ACM, (2007)Synergistic use of multiple on-chip networks for ultra-low latency and scalable distributed routing reconfiguration., , и . DATE, стр. 806-811. ACM, (2015)A fast centralized computation routing algorithm for self-configuring NoC systems., , , и . HiPC, стр. 1-10. IEEE Computer Society, (2011)Transient and Permanent Error Control for High-End Multiprocessor Systems-on-Chip., , , и . NOCS, стр. 169-176. IEEE Computer Society, (2012)Yield-oriented evaluation methodology of network-on-chip routing implementations., , , , , , , , и . SoC, стр. 100-105. IEEE, (2009)