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Optimizing time and space multiplexed computation in a dynamically reconfigurable processor., , , , , , и . FPT, стр. 106-111. IEEE, (2013)Stream applications on the dynamically reconfigurable processor., , , , , , , , , и 1 other автор(ы). FPT, стр. 137-144. IEEE, (2004)An Adaptive Cryptographic Accelerator for IPsec on Dynamically Reconfigurable Processor., , , , , и . FPT, стр. 163-170. IEEE, (2005)Implementing core tasks of JPEG2000 Encoder on the Dynamically Reconfigurable Processor., , , , , и . ARCS Workshops, стр. 12-18. VDE Verlag, (2005)Implementing and Evaluating Stream Applications on the Dynamically Reconfigurable Processor., , , , , , , , , и 3 other автор(ы). FCCM, стр. 328-329. IEEE Computer Society, (2004)High-level synthesis challenges and solutions for a dynamically reconfigurable processor., , , , , и . ICCAD, стр. 702-708. ACM, (2006)Iterative Synthesis Methods Estimating Programmable-Wire Congestion in a Dynamically Reconfigurable Processor., , , , и . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 94-A (12): 2619-2627 (2011)Wire congestion aware synthesis for a dynamically reconfigurable processor., , , , и . FPT, стр. 300-303. IEEE, (2010)Panel discussions: Impact on society by fusion and harmony of mobile devices, servers, and networks - Their direction of evolutions and optimal roles., , , , и . COOL Chips, стр. 1-2. IEEE Computer Society, (2011)An optimal chip compaction method based on shortest path algorithm with automatic jog insertion., , , и . ICCAD, стр. 162-165. IEEE Computer Society / ACM, (1992)