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Optimizing time and space multiplexed computation in a dynamically reconfigurable processor.

, , , , , , and . FPT, page 106-111. IEEE, (2013)

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Optimizing time and space multiplexed computation in a dynamically reconfigurable processor., , , , , , and . FPT, page 106-111. IEEE, (2013)Wire congestion aware synthesis for a dynamically reconfigurable processor., , , , and . FPT, page 300-303. IEEE, (2010)An adaptive Viterbi decoder on the dynamically reconfigurable processor., , , , and . FPT, page 285-288. IEEE, (2006)Iterative Synthesis Methods Estimating Programmable-Wire Congestion in a Dynamically Reconfigurable Processor., , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 94-A (12): 2619-2627 (2011)New Generation Dynamically Reconfigurable Processor Technology for Accelerating Embedded AI Applications., , , , , , , , and . VLSI Circuits, page 41-42. IEEE, (2018)High-level Synthesis Challenges for Mapping a Complete Program on a Dynamically Reconfigurable Processor., , , , and . Inf. Media Technol., 5 (2): 398-411 (2010)High-level synthesis challenges and solutions for a dynamically reconfigurable processor., , , , , and . ICCAD, page 702-708. ACM, (2006)A CMOS Image Sensor and an AI Accelerator for Realizing Edge-Computing-Based Surveillance Camera Systems., , , , , , , , and . VLSI Circuits, page 1-2. IEEE, (2021)20.3 A 23.9TOPS/W @ 0.8V, 130TOPS AI Accelerator with 16× Performance-Accelerable Pruning in 14nm Heterogeneous Embedded MPU for Real-Time Robot Applications., , , , , , , and . ISSCC, page 364-366. IEEE, (2024)Stream applications on the dynamically reconfigurable processor., , , , , , , , , and 1 other author(s). FPT, page 137-144. IEEE, (2004)