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Slope interconnect effort: gate-interconnect interdependentdelay model for CMOS logic gates.

M. Hwang, S. Jung, and K. Roy. ISLPED, page 387-390. ACM, (2007)

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Seong-Jung Kim

Ki-Chang Seong

Seunghyeon Seong

Nak-Hyon Seong

Hong-Jae Seong

Other publications of authors with the same name

MTJ based non-volatile flip-flop in deep submicron technology.Y. Jung, J. Kim, K. Ryu, S. Jung, J. Kim, and S. Kang. ISOCC, page 424-427. IEEE, (2011)Noise-aware power optimization for on-chip interconnect.K. Kim, S. Jung, U. Narayanan, C. Liu, and S. Kang. ISLPED, page 108-113. ACM, (2000)An MTJ-based non-volatile flip-flop for high-performance SoC.Y. Jung, J. Kim, K. Ryu, J. Kim, S. Kang, and S. Jung. I. J. Circuit Theory and Applications, 42 (4): 394-406 (2014)Transistor sizing for reliable domino logic design in dual threshold voltage technologies.S. Jung, K. Kim, and S. Kang. ACM Great Lakes Symposium on VLSI, page 133-138. ACM, (2001)Low-swing clock domino logic incorporating dual supply and dual threshold voltages.S. Jung, K. Kim, and S. Kang. DAC, page 467-472. ACM, (2002)SRAM Write Assist Circuit Using Cell Supply Voltage Self-Collapse With Bitline Charge Sharing for Near-Threshold Operation.K. Cho, J. Park, K. Kim, T. Oh, and S. Jung. IEEE Trans. Circuits Syst. II Express Briefs, 69 (3): 1567-1571 (2022)A Highly Integrated Crosspoint Array Using Self-rectifying FTJ for Dual-mode Operations: CAM and PUF.S. Lim, Y. Goh, Y. Lee, D. Ko, J. Hwang, M. Kim, Y. Jeong, H. Shin, S. Jeon, and S. Jung. ESSCIRC, page 113-116. IEEE, (2022)Thyristor-Based Volatile Memory in Nano-Scale CMOS.R. Roy, F. Nemati, K. Young, B. Bateman, R. Chopra, S. Jung, C. Show, and H. Cho. ISSCC, page 2612-2621. IEEE, (2006)Intrinsic Capacitance based Multi bit Computing in Memory.Y. Lee, M. Yeo, S. Cho, and S. Jung. ISOCC, page 361-362. IEEE, (2021)Pseudo NMOS based sense amplifier for high speed single-ended SRAM.H. Jeong, T. Kim, S. Jung, T. Song, and G. Kim. ICECS, page 331-334. IEEE, (2014)

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Disambiguation of "Jung, Seong-Ook"

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Slope interconnect effort: gate-interconnect interdependentdelay model for CMOS logic gates.

Please choose a person to relate this publication to

Seong-Jung Kim

Ki-Chang Seong

Seunghyeon Seong

Nak-Hyon Seong

Hong-Jae Seong

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Jung, Seong-Ook"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Slope interconnect effort: gate-interconnect interdependentdelay model for CMOS logic gates.

Please choose a person to relate this publication to

Seong-Jung Kim

Ki-Chang Seong

Seunghyeon Seong

Nak-Hyon Seong

Hong-Jae Seong

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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Slope interconnect effort: gate-interconnect interdependentdelay model for CMOS logic gates.