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Disambiguation of "Mao, Mengjie"

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FACRA: Flexible-Core Architecture Chip Resource Abstractor.

, , , , , , and . PDCAT, page 440-447. IEEE Computer Society, (2010)

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Tongsheng Mao

Yiqin Mao

Ning-hui Mao

Lei Mao

Zhengrong Mao

 

Other publications of authors with the same name

An efficient STT-RAM-based register file in GPU architectures., , , , and . ASP-DAC, page 490-495. IEEE, (2015)Heterogeneous systems with reconfigurable neuromorphic computing accelerators., , , , , , and . ISCAS, page 125-128. IEEE, (2016)TEMP: thread batch enabled memory partitioning for GPU., , , , , , and . DAC, page 65:1-65:6. ACM, (2016)Distributed replay protocol for distributed uniprocessors., , , , , , and . ICS, page 3-14. ACM, (2012)FACRA: Flexible-Core Architecture Chip Resource Abstractor., , , , , , and . PDCAT, page 440-447. IEEE Computer Society, (2010)CD-ECC: content-dependent error correction codes for combating asymmetric nonvolatile memory operation errors., , , , , and . ICCAD, page 1-8. IEEE, (2013)Prefetching techniques for STT-RAM based last-level cache in CMP systems., , , , and . ASP-DAC, page 67-72. IEEE, (2014)Exploration of GPGPU Register File Architecture Using Domain-wall-shift-write based Racetrack Memory., , , , and . DAC, page 196:1-196:6. ACM, (2014)Harmonica: A Framework of Heterogeneous Computing Systems With Memristor-Based Neuromorphic Computing Accelerators., , , , , , , , , and 1 other author(s). IEEE Trans. Circuits Syst. I Regul. Pap., 63-I (5): 617-628 (2016)State-Restrict MLC STT-RAM Designs for High-Reliable High-Performance Memory System., , , and . DAC, page 35:1-35:6. ACM, (2014)