Author of the publication

Relaxed Min-Max Decoder Architectures for Nonbinary Low-Density Parity-Check Codes.

, and . IEEE Trans. Very Large Scale Integr. Syst., 21 (11): 2010-2023 (2013)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Reduced-latency scheduling scheme for min-max non-binary LDPC decoding., and . APCCAS, page 414-417. IEEE, (2010)Error correction for multi-level NAND flash memory using Reed-Solomon codes., , and . SiPS, page 94-99. IEEE, (2008)High-speed architecture for image reconstruction based on compressive sensing., and . ICASSP, page 1574-1577. IEEE, (2010)Efficient architecture for generalized minimum-distance decoder of Reed-Solomon codes., and . ICASSP, page 1502-1505. IEEE, (2010)Relaxed Min-Max Decoder Architectures for Nonbinary Low-Density Parity-Check Codes., and . IEEE Trans. Very Large Scale Integr. Syst., 21 (11): 2010-2023 (2013)Efficient VLSI Architecture for Soft-Decision Decoding of Reed-Solomon Codes., and . IEEE Trans. Circuits Syst. I Regul. Pap., 55-I (10): 3050-3062 (2008)Fast Nested Key Equation Solvers for Generalized Integrated Interleaved Decoder., and . IEEE Trans. Circuits Syst. I Regul. Pap., 68 (1): 483-495 (2021)Efficient Hardware Implementation Architectures for Long Integer Modular Multiplication over General Solinas Prime., , and . J. Signal Process. Syst., 94 (10): 1067-1082 (2022)Generalized Backward Interpolation for Algebraic Soft-Decision Decoding of Reed-Solomon Codes., and . IEEE Trans. Commun., 61 (1): 13-23 (2013)Reduced-Complexity Key Equation Solvers for Generalized Integrated Interleaved BCH Decoders., and . IEEE Trans. Circuits Syst., 67-I (12): 5520-5529 (2020)