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A high-performance CABAC encoder architecture for HEVC and H.264/AVC.

, , , и . ICIP, стр. 1568-1572. IEEE, (2013)

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Zhou Zhou

Zhou Zhou

Jiyang Zhou

Zuliang Zhou

Chunshan Zhou

 

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Merge mode based fast inter prediction for HEVC., , , и . VCIP, стр. 1-4. IEEE, (2015)Interlaced asymmetric search range assignment for bidirectional motion estimation., , и . ICIP, стр. 1557-1560. IEEE, (2012)An independent bandwidth reduction device for HEVC VLSI video system., , , , и . ISCAS, стр. 609-612. IEEE, (2015)Approximate-DCT-Derived Measurement Matrices with Row-Operation-Based Measurement Compression and its VLSI Architecture for Compressed Sensing., , , и . IEICE Trans. Electron., 101-C (4): 263-272 (2018)An area-efficient 4/8/16/32-point inverse DCT architecture for UHDTV HEVC decoder., , , , и . VCIP, стр. 197-200. IEEE, (2014)A High Performance HEVC De-Blocking Filter and SAO Architecture for UHDTV Decoder., , и . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 96-A (12): 2612-2622 (2013)A Bandwidth Reduction Scheme and Its VLSI Implementation for H.264/AVC Motion Vector Decoding., , , и . PCM (2), том 6298 из Lecture Notes in Computer Science, стр. 52-61. Springer, (2010)A 16-65 cycles/MB H.264/AVC motion compensation architecture for Quad-HD applications., , , и . EUSIPCO, стр. 729-733. IEEE, (2011)A Low-Complexity HEVC Intra Prediction Algorithm Based on Level and Mode Filtering., , и . ICME, стр. 1085-1090. IEEE Computer Society, (2012)An FPGA-based 4K UHDTV H.264/AVC video decoder., , и . ICME Workshops, стр. 1-4. IEEE Computer Society, (2013)