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Hardware transactional memory with software-defined conflicts., , , , , , , и . ACM Trans. Archit. Code Optim., 8 (4): 31:1-31:20 (2012)Runtime-assisted cache coherence deactivation in task parallel programs., , , , и . SC, стр. 35:1-35:12. IEEE / ACM, (2018)Increasing Memory Bandwidth with Wide Buses: Compiler, Hardware and Performance Trade-Offs., , , и . International Conference on Supercomputing, стр. 12-19. ACM, (1997)Automatic generation of loop scheduling for VLIW., , , и . PACT, стр. 306-309. IFIP Working Group on Algol / ACM, (1995)Initial Evaluation of Multimedia Extensions on VLIW Architectures., и . SAMOS, том 3133 из Lecture Notes in Computer Science, стр. 403-412. Springer, (2004)Performance and Power Evaluation of Clustered VLIW Processors with Wide Functional Units., , , , и . SAMOS, том 3133 из Lecture Notes in Computer Science, стр. 88-97. Springer, (2004)Quantifying the Potential Task-Based Dataflow Parallelism in MPI Applications., , , , и . Euro-Par (1), том 6852 из Lecture Notes in Computer Science, стр. 39-51. Springer, (2011)Memory Access Synchronization in Vector Multiprocessors., , и . CONPAR, том 854 из Lecture Notes in Computer Science, стр. 414-425. Springer, (1994)Parallel Computer Architecture., , , и . Euro-Par, том 1900 из Lecture Notes in Computer Science, стр. 537-538. Springer, (2000)Topic 15+20: Multimedia and Embedded Systems., , , и . Euro-Par, том 2150 из Lecture Notes in Computer Science, стр. 651-652. Springer, (2001)