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Disambiguation of "Yoshimura, Chihiro"

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Implementation and Evaluation of FPGA-based Annealing Processor for Ising Model by use of Resource Sharing.

, , , and . Int. J. Netw. Comput., 7 (2): 154-172 (2017)

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Tateo Yoshimura

Tadasuke Yoshimura

 

Other publications of authors with the same name

Implementation and Evaluation of FPGA-based Annealing Processor for Ising Model by use of Resource Sharing., , , and . Int. J. Netw. Comput., 7 (2): 154-172 (2017)A 1.3-Mbit Annealing System Composed of Fully-Synchronized 9-board x 9-chip x 16-kbit Annealing Processor Chips for Large-Scale Combinatorial Optimization Problems., , , , and . A-SSCC, page 1-3. IEEE, (2021)Dynamical Perception-Action Loop Formation with Developmental Embodiment for Hierarchical Active Inference., , , , , and . IWAI, volume 1915 of Communications in Computer and Information Science, page 14-28. Springer, (2023)Accelerator Chip for Ground-state Searches of Ising Model with Asynchronous Random Pulse Distribution., , , , , and . Int. J. Netw. Comput., 6 (2): 195-211 (2016)Spatial computing architecture using randomness of memory cell stability under voltage control., , , and . ECCTD, page 1-4. IEEE, (2013)Quantum Computer Architecture for Quantum Error Correction with Distributing Process to Multiple Temperature Layers., , and . candar, page 196-202. IEEE, (2023)4.6 A 144Kb Annealing System Composed of 9× 16Kb Annealing Processor Chips with Scalable Chip-to-Chip Connections for Large-Scale Combinatorial Optimization Problems., , , , , , , and . ISSCC, page 64-66. IEEE, (2021)Computing architecture to perform approximated simulated annealing for Ising models., , , and . ICRC, page 1-8. IEEE Computer Society, (2016)24.3 20k-spin Ising chip for combinational optimization problem with CMOS annealing., , , , , and . ISSCC, page 1-3. IEEE, (2015)Response Style Characterization for Repeated Measures Using the Visual Analogue Scale., , , , , and . IEEE Access, (2024)