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Disambiguation of "Yamaoka, Masanao"

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A 1.3-Mbit Annealing System Composed of Fully-Synchronized 9-board x 9-chip x 16-kbit Annealing Processor Chips for Large-Scale Combinatorial Optimization Problems.

, , , , and . A-SSCC, page 1-3. IEEE, (2021)

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Hideki Yamaoka

So Yamaoka

 

Other publications of authors with the same name

65nm Low-Power High-Density SRAM Operable at 1.0V under 3σ Systematic Variation Using Separate Vth Monitoring and Body Bias for NMOS and PMOS., , , and . ISSCC, page 384-385. IEEE, (2008)Efficient Ising Model Mapping to Solving Slot Placement Problem., , , , , , , and . ICCE, page 1-6. IEEE, (2019)Low-voltage limitations of deep-sub-100-nm CMOS LSIs: view of memory designers., , and . ACM Great Lakes Symposium on VLSI, page 529-533. ACM, (2007)Technology/circuits joint evening panel discussion semiconductor industry in 2020: Evolution or revolution?, , , , , , , , , and 3 other author(s). VLSIC, page 22-. IEEE, (2015)Graph Minors from Simulated Annealing for Annealing Machines with Sparse Connectivity., , , , , , , , , and . TPNC, volume 11324 of Lecture Notes in Computer Science, page 111-123. Springer, (2018)A 40-nm low-power SRAM with multi-stage replica-bitline technique for reducing timing variation., , , , , and . CICC, page 701-704. IEEE, (2009)Implementation and Evaluation of FPGA-based Annealing Processor for Ising Model by use of Resource Sharing., , , and . Int. J. Netw. Comput., 7 (2): 154-172 (2017)Operating-margin-improved SRAM with column-at-a-time body-bias control technique., and . ESSCIRC, page 396-399. IEEE, (2007)A 1.3-Mbit Annealing System Composed of Fully-Synchronized 9-board x 9-chip x 16-kbit Annealing Processor Chips for Large-Scale Combinatorial Optimization Problems., , , , and . A-SSCC, page 1-3. IEEE, (2021)A Detailed Vth-Variation Analysis for Sub-100-nm Embedded SRAM Design., and . SoCC, page 315-318. IEEE, (2006)