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Disambiguation of "Cao, Yuefeng"

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A 91.0-dB SFDR Single-Coarse Dual-Fine Pipelined-SAR ADC With Split-Based Background Calibration in 28-nm CMOS.

, , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 68 (2): 641-654 (2021)

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Yuefeng Ruan

Weixun Cao

Ou Cao

Jialin Cao

Xinyu Cao

 

Other publications of authors with the same name

Use Multilayer Perceptron in Calibrating Multistage Non-linearity of Split Pipelined-ADC., , , and . ISCAS, page 1-5. IEEE, (2018)An 11b 80MS/s SAR ADC With Speed-Enhanced SAR Logic and High-Linearity CDAC., , , , and . APCCAS, page 18-21. IEEE, (2018)A Single-Channel 12b 2GS/s PVT-Robust Pipelined ADC with Critically Damped Ring Amplifier and Time-Domain Quantizer., , , , and . ISSCC, page 170-171. IEEE, (2023)Machine Learning Based Prior-Knowledge-Free Calibration for Split Pipelined-SAR ADCs with Open-Loop Amplifiers Achieving 93.7-dB SFDR., , , , , and . ESSCIRC, page 189-192. IEEE, (2019)A 800 MS/s, 12-Bit, Ringamp-Based SAR assisted Pipeline ADC with Gain Error Cancellation., , , , and . ISCAS, page 1-4. IEEE, (2018)An Operational Amplifier Assisted Input Buffer and An Improved Bootstrapped Switch for High-Speed and High-Resolution ADCs., , , , and . ISCAS, page 1-5. IEEE, (2018)A 10b 250MS/s SAR ADC with Speed-Enhanced SAR Logic and Free Time More Than a Half of Sampling Period., , , and . ASICON, page 1-4. IEEE, (2019)Bad Data Identification Based on Optimized Local Outlier Detection Algorithm., , and . GRMSE (1), volume 698 of Communications in Computer and Information Science, page 203-212. Springer, (2016)A 91.0-dB SFDR Single-Coarse Dual-Fine Pipelined-SAR ADC With Split-Based Background Calibration in 28-nm CMOS., , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 68 (2): 641-654 (2021)22.1 A 12GS/s 12b 4× Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer., , , , and . ISSCC, page 388-390. IEEE, (2024)