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A 91.0-dB SFDR Single-Coarse Dual-Fine Pipelined-SAR ADC With Split-Based Background Calibration in 28-nm CMOS.

, , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 68 (2): 641-654 (2021)

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An Operational Amplifier Assisted Input Buffer and An Improved Bootstrapped Switch for High-Speed and High-Resolution ADCs., , , , and . ISCAS, page 1-5. IEEE, (2018)A 12-Bit ENOB 8MHz BW Noise-Shaping SAR ADC Using High-Speed Switches., , , , and . MWSCAS, page 392-395. IEEE, (2018)A 625MS/s, 12-Bit, SAR Assisted Pipeline ADC with Effective Gain Analysis for Inter-stage Ringamps., , , , , , and . ESSCIRC, page 197-200. IEEE, (2019)A 4.75-64 Gb/s PAM-4 Wireline Transmitter with 3-tap FFE in 28-nm CMOS., , , , , and . ISCAS, page 1-5. IEEE, (2023)An Input Buffer for 4 GS/s 14-b Time-Interleaved ADC., , , , and . ASICON, page 1-4. IEEE, (2021)Complexity-Reduced Joint Calibration for Nonlinearity and I/Q Imbalance in Direct-Conversion Transmitters., , , and . ASICON, page 1-4. IEEE, (2023)Digital Calibration of Capacitor Mismatch and Gain Error in Pipelined SAR ADCs., , , , and . ASICON, page 1-4. IEEE, (2021)A 7.8 fJ/conversion-step 9-bit 400-MS/s single-channel SAR ADC with fast control logic., , , and . APCCAS, page 42-45. IEEE, (2018)A 200MS/s, 11 bit SAR-assisted pipeline ADC with bias-enhanced ring amplifier., , , , and . ISCAS, page 1-4. IEEE, (2017)An 11b 80MS/s SAR ADC With Speed-Enhanced SAR Logic and High-Linearity CDAC., , , , and . APCCAS, page 18-21. IEEE, (2018)