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Architecture of a Memory Manager for an MPEG-2 Video Decoding Circuit.

, , and . VLSI Signal Processing, 20 (3): 251-265 (1998)

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Efficient Parallelisation of an MPEG-2 Codec on a TMS320C80 Video Processor., and . ICIP (3), page 977-980. IEEE Computer Society, (1998)Architecture of a Memory Manager for an MPEG-2 Video Decoding Circuit., , and . VLSI Signal Processing, 20 (3): 251-265 (1998)Communications Challenges in the Celtic-BOSS Project., , , , , , , , , and 2 other author(s). NEW2AN, volume 4712 of Lecture Notes in Computer Science, page 431-442. Springer, (2007)