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Normalization at the arithmetic bit level., , and . DAC, page 457-462. ACM, (2005)Arithmetic Constraints in SAT-based Property Checking., , , and . MBMV, page 91-100. Shaker, (2007)Compositional Fault Propagation Analysis in Embedded Systems using Abstract Interpretation., , , , and . MBMV, page 1-4. VDE/IEEE, (2022)Fast and Accurate Model-Driven FPGA-based System-Level Fault Emulation., , , , , , , and . VLSI-SoC, page 1-6. IEEE, (2022)MetaFS: Model-driven Fault Simulation Framework., , , , , , and . DFT, page 1-4. IEEE, (2022)Record & play: a structural fixed point iteration for sequential circuit verification., and . ICCAD, page 394-399. IEEE Computer Society / ACM, (1997)Symbolic quick error detection using symbolic initial state for pre-silicon verification., , , , , , and . DATE, page 55-60. IEEE, (2018)Data-Oblivious and Performant: On Designing Security-Conscious Hardware., , , , , , , and . LATS, page 1-6. IEEE, (2024)A New Verification Technique for Custom-Designed Components at the Arithmetic Bit Level., , , , , and . FDL (Selected Papers), volume 36 of Lecture Notes in Electrical Engineering, page 257-272. (2008)A computational model for SAT-based verification of hardware-dependent low-level embedded system software., , , , , and . ASP-DAC, page 711-716. IEEE, (2013)